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copyright ? 201 3 future technology devices international limited 1 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 future technology devices international ltd . ft240x ( usb 8 - bit fifo ic ) the ft240x is a usb to parallel fifo interface with the following advanced features: ? single chip usb to parallel fifo bidirectional data transfer interface . ? entire usb protocol handled on the chip. no usb specific firmware programming required. ? fully integrated 2048 byte multi - time - programmable (mtp) memory, storing device descriptors and fifo i/o configuration. ? fully integrated clock generation with no external crystal required plus option al clock output selection enabling glue - less interface to external mcu or fpga. ? data transfer rates up to 1mbyte / second. ? 512 byte receive buffer and 512 byte transmit buffer utilising buffer smoothing technology to allow for high data throughput. ? ftdis ? configurable fifo interface i/o pins. ? synchronous and asynchronous bit bang interface options . ? u sb battery charger detection. allows for usb peripheral devices to detect the presence of a higher power source to enable improved charging. ? device supplied pre - programmed with unique usb serial number. ? usb power configurations; s upports bus - powered, self - powered and bus - powered with power switching . ? integrated +3.3v level converter for usb i/o. ? true 3.3 v cmos drive output and ttl input ; operates down to 1v8 with external pull - ups. tolerant of 5v input. ? configurable i /o pin output drive strength ; 4 ma(min) and 16 ma(max). ? integrated p ower - on - reset circuit. ? fully integrated avcc supply filtering - no external filtering required. ? + 5v single supply operation. ? internal 3v3/1v8 ldo regulators ? low operating and usb suspend current ; 8ma (active - typ) and 125ua (suspend - typ) . ? uhci/ohci/ehci hos t controller compatible. ? usb 2.0 full speed c apable . ? extended operating temperature range; - 40 to 85 ? ? available in compact pb - free 2 4 pin ssop and qfn - 2 4 packages (both rohs compliant). neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or re produced in any material or electronic form without the prior written consent of the copyright holder. this product and its documen tation are supplied on an as - is basis and no warranty as to their suitability for any particular purpose is either made or implied. future technology devices international ltd will not accept any claim for damages howsoever arising as a result of use or fa ilure of this product. your statutory rights are not affected. this product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injur y. this document provides preliminary information that may be subject to change without notice. no freedom to use patents or other intellectual property rights is implied by the publication of this document. future technology devices international ltd, uni t 1, 2 seaward place, centurion business park, glasgow g41 1hh united kingdom . scotland registered company number: sc136640
copyright ? 201 3 future technology devices international limited 2 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 1 typical applications ? upgrading legacy peripherals to usb ? utilising usb to add system modularity ? incorporate usb interface to enable pc transfers for development system communication ? cellular and cordless phone usb data transfer cables and interfaces ? interfacing mcu/pld/fpga based designs to usb ? usb audio and low bandwidth video data transfer ? usb sm art card readers ? usb industrial control ? usb mp3 player interface ? usb flash card reader and writers ? set top box pc - usb interface ? usb digital camera interface ? usb software and hardware encryption dongles ? usb instrumentation ? usb dongle implementations for software / hardware encryption and wireless modules ? provides detection of dedicated charging ports for charging batteries in portable devices. 1.1 driver support royalty free virtual com port (vcp) drivers for... ? windows 8 32,64 - bit ? windows 7 32,64 - bit ? windows vista and vista 64 - bit ? windows xp and xp 64 - bit ? windows xp embedded ? server 2003, xp and server 2008 ? windows ce 4.2, 5.0 and 6.0 ? mac os - x ? linux 3.2 and greater ? android royalty free d2xx direct drivers (usb drivers + dll s/w interface) ? windows 8 32,64 - bit ? windows 7 32,64 - bit ? windows vista and vista 64 - bit ? windows xp and xp 64 - bit ? windows xp embedded ? server 2003, xp and server 2008 ? windows ce 4.2, 5.0 and 6.0 ? mac os - x ? linux 2. 6 and greater ? android the drivers listed above are all available to download for free from ftdi website ( www.ftdichip.com ) . various 3rd party drivers are also available for other operating s ystems - see ftdi website ( www.ftdichip.com ) for details. for driver installation, please refer to the application note an232b - 10 . for driver installation, please refer to http://www.ftdichip.com/documents/installguides.htm 1.2 part numbers part number package ft240x q - x 24 pin qfn ft240xs - x 2 4 pin ssop note: packaging codes for x is: - r: taped and reel, (ssop is 3 ,000pcs per reel, qfn is 5 ,000pcs per reel). - u : tube packing, 58 pcs per tube (ssop only) - t: tray packing, 490pcs per tray (qfn only) for example: ft240x q - r is 5 ,000pcs taped and reel packing
copyright ? 201 3 future technology devices international limited 3 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 1.3 usb compliant the ft240x is fully compliant with the usb 2.0 specification and has been given the usb - if test - id (tid) 4000 1466 (rev d ).
copyright ? 201 3 future technology devices international limited 4 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 2 ft240x block diagram figure 2 . 1 ft240x block diagram for a description of each function please refer to section 4. 3 . 3 v o l t l d o r e g u l a t o r 1 . 8 v o l t l d o r e g u l a t o r u s b t r a n s c e i v e r w i t h i n t e g r a t e d 1 . 5 k p u l l u p s a n d b a t t e r y c h a r g e d e t e c t i o n u s b d p l l i n t e r n a l 1 2 m h z o s c i l l a t o r x 4 c l o c k m u l t i p l i e r s e r i a l i n t e r f a c e e n g i n e ( s i e ) u s b p r o t o c o l e n g i n e f i f o i n t e r f a c e c o n t r o l l e r r e s e t g e n e r a t o r f i f o t x b u f f e r ( 5 1 2 b y t e s ) f i f o r x b u f f e r ( 5 1 2 b y t e s ) i n t e r n a l m t p m e m o r y 4 8 m h z g n d r e s e t # t o u s b t r a n s c e i v e r c e l l 3 v 3 o u t v c c i o 3 v 3 o u t v c c u s b d p u s b d m 1 v 8 i n t e r n a l c o r e s u p p l y d a t a [ 0 ] d a t a [ 1 ] d a t a [ 2 ] d a t a [ 3 ] d a t a [ 4 ] d a t a [ 5 ] d a t a [ 6 ] d a t a [ 7 ] r x f # t x e # r d # w r s i w u a c b u s 5 c b u s 6
copyright ? 201 3 future technology devices international limited 5 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 table of contents 1 typical applications ................................ ................................ ...... 2 1.1 driver support ................................ ................................ .................... 2 1.2 part numbers ................................ ................................ ...................... 2 1.3 usb compliant ................................ ................................ .................... 3 2 ft240x block diagram ................................ ................................ . 4 3 device pin out and signal description ................................ .......... 7 3.1 24 - ld ssop package ................................ ................................ .......... 7 3.2 ssop package pin out description ................................ ...................... 7 3.3 qfn - 24 package ................................ ................................ ................. 9 3.4 qfn - 24 package signal description ................................ .................... 9 3.5 cbus signal options ................................ ................................ ......... 11 3.6 ft240x fifo read timing diagrams ................................ ................ 12 3.7 ft240x fifo write timing diagrams ................................ .............. 13 4 function description ................................ ................................ ... 14 4.1 key features ................................ ................................ ..................... 14 4.2 function al block descriptions ................................ ........................... 15 5 devices characteristics and ratings ................................ ........... 16 5.1 absolute maximum ratings ................................ ............................... 16 5.2 esd and latch - up specifications ................................ ....................... 16 5.3 dc characteristics ................................ ................................ ............. 17 5.4 mtp memory reliability characteristics ................................ ............ 21 5.5 internal clock characteristics ................................ ........................... 21 6 usb power configurations ................................ .......................... 22 6.1 usb bus powered configuration ................................ ...................... 22 6.2 self powered configuration ................................ .............................. 23 6.3 usb bus powered with power switching configuration .................... 24 7 application examples ................................ ................................ . 25 7.1 usb to mcu fifo interface ................................ ............................... 25 7.2 battery charge detection ................................ ................................ .. 26 8 internal mtp memory configuration ................................ ........... 28 8.1 default values ................................ ................................ .................. 28 8.2 methods of programming the mtp memory ................................ ....... 29 8.2.1 programming the mtp memory over usb ................................ ................................ ...... 29 8.3 memory map ................................ ................................ ..................... 30 9 package parameters ................................ ................................ ... 31
copyright ? 201 3 future technology devices international limited 6 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 9.1 ssop - 24 package mechanical dimensions ................................ ........ 31 9.2 ssop - 24 package markings ................................ .............................. 32 9.3 qfn - 24 package mechanical dimensions ................................ .......... 33 9.4 qfn - 24 package markings ................................ ................................ 34 9.5 solder reflow profile ................................ ................................ ........ 35 10 contact information ................................ ................................ ... 36 appendix a - references ................................ ................................ ............ 37 appe ndix b - list of figures and tables ................................ ..................... 38 appendix c - revision history ................................ ................................ .... 40
copyright ? 201 3 future technology devices international limited 7 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 3 device pin out and signal description 3.1 24 - ld ssop package figure 3 . 1 ssop package pin out and schematic symbol 3.2 ssop package pin out description note: the convention used throughou t this document for active low signals is the signal name followed by a # pin no. name type description 1 3 usbdp i/o usb data signal plus, incorporating 1.5k pull up resistor to 3.3v. usb data signal minus. table 3 . 1 usb interface group pin no. name type description 3 vccio pwr 1v8 - 3v3 supply for the io cells 6 , 19 gnd pwr device ground supply pins 15 ** 3v3out output 3v3 output at 50ma. may be used to power vccio . when vcc is 3v3; pin 15 is an input pin and should be connected to pin 18 . 18 ** vcc pwr +5v (or 3v3) supply to the device core. 17 v core pwr +1v8 output. may be left unterminated table 3 . 2 power and ground group ** if vcc is 3v3 then 3v3out must also be driven with 3v3 input data1 4 data7 5 g n d 6 data5 7 data6 8 data3 9 si/wu# 10 rd# 11 wr# 12 usbdp 13 usbdm 14 3v3out 15 v c o r e 1 7 reset# 16 v c c 1 8 g n d 1 9 txe# 20 rxf# 21 cbus6 22 cbus5 23 data0 24 data4 1 data2 2 v c c i o 3
copyright ? 201 3 future technology devices international limited 8 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 pin no. name type description 1 6 reset# input active low reset pin. this can be used by an external device to reset the ft240x . if not required can be left unconnected, or pulled up to vcc. 10 siwu# input active low input. may be used to flush the ic buffer back to the pc (send immediate) or if the pc is in suspend mode it can be used as a wake up signal. 23 cbus5 i/o configurable cbus i/o pin. function of this pin is configured in the device mtp memory . see cbus signal options, table 3 . 9 . 22 cbus6 i/o configurable cbus i/o pin. function of this pin is configured in the device mtp memory . see cbus signal options, table 3 . 9 . table 3 . 3 miscellaneous signal group pin no. name type description 24 d0 i/o fifo data bus bit 0 4 d 1 i/o fifo data bus bit 1 2 d2 i/o fifo data bus bit 2 9 d 3 i/o fifo data bus bit 3 1 d 4 i/o fifo data bus bit 4 7 d5 i/o fifo data bus bit 5 8 d6 i/o fifo data bus bit 6 5 d 7 i/o fifo data bus bit 7 1 1 rd# input enables the current fifo data byte on d0...d7 when low. fetched the next fifo data byte (if available) from the receive fifo buffer when rd# goes from high to low. see section 3.6 for timing diagram. 1 2 wr input writes the data byte on the d0...d7 pins into the transmit fifo buffer when wr goes from high to low. see section 3.7 for timing diagram. 2 0 txe# output when high, do not write data into the fifo. when low, data can be written into the fifo by strobing wr high, then low. during reset this signal pin is tri - state. see section 3.7 for timing diagram. 2 1 rxf # output when high, do not read data from the fifo. when low, there is data available in the fifo which can be read by strobing rd# low, then high again. during reset this signal pin is tri - state. see section 3.6 for timing diagram. if the remote wakeup option is enabled in the internal mtp memory , during usb suspend mode (pwren# = 1) rxf# becomes an input. this can be used to wake up the usb host from suspend mode by strobing this pin low for a minimum of 20ms which will cause the device to request a resume on the usb bus. table 3 . 4 fifo interface group (see note 2 ) notes: when used in input mode, the input pins are pulled to vccio via internal 200k resistors. these pins can be programmed to gently pull low during usb suspend (pwren# = 1) by setting an option in the internal mtp memory .
copyright ? 201 3 future technology devices international limited 9 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 3.3 qfn - 24 package figure 3 . 2 qfn - 24 package pin out and schematic symbol 3.4 qfn - 24 package signal description note: the co nvention used throughout this document for active low signals is the signal name followed by a # pin no. name type description 1 0 usbdp i/o usb data signal plus, incorporating 1.5k pull up resistor to 3.3v. usb data signal minus. table 3 . 5 usb interface group pin no. name type description 24 vccio pwr 1v8 - 3v3 supply for the io cells 3, 16 gnd pwr device ground supply pins 12 ** 3v3out output 3v3 output at 50ma. may be used to power vccio . when vcc is 3v3; pin 12 is an input pin and should be connected to pin 15 . 15 ** vcc pwr +5v (or 3v3) supply to the device core. 14 v core pwr +1v8 output. may be left unterminated table 3 . 6 power and ground group *pin 25 is the centre pad on package base. connect to gnd. ** if vcc is 3v3 then 3v3out must also be driven with 3v3 input v c c i o 2 4 data7 2 data4 22 g n d 3 data5 4 data2 23 data3 6 si/wu# 7 rd# 8 wr# 9 usbdp 10 usbdm 11 3v3out 12 reset# 13 v c c 1 5 txe# 17 rxf# 18 cbus5 20 g n d 1 6 cbus6 19 data0 21 data6 5 data1 1 v c o r e 1 4 g n d 2 5
copyright ? 201 3 future technology devices international limited 10 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 pin no. name type description 1 3 reset# input active low reset pin. this can be used by an external device to reset the ft240x . if not required can be left unconnected, or pulled up to vcc. 7 siwu # input active low input. may be used to flush the ic buffer back to the pc (send immediate) or if the pc is in suspend mode it can be used as a wake up signal. 20 cbus5 i/o configurable cbus i/o pin. function of this pin is configured in the device mtp memory . see cbus signal options, table 3 . 9 . 19 cbus6 i/o configurable cbus i/o pin. function of this pin is configured in the device mtp memory . see cbus signal options, table 3 . 9 . table 3 . 7 miscellaneous signal group pi n no. name type description 21 d0 i/o fifo data bus bit 0 1 d 1 i/o fifo data bus bit 1 23 d2 i/o fifo data bus bit 2 6 d 3 i/o fifo data bus bit 3 22 d 4 i/o fifo data bus bit 4 4 d5 i/o fifo data bus bit 5 5 d6 i/o fifo data bus bit 6 2 d 7 i/o fifo data bus bit 7 8 rd# input enables the current fifo data byte on d0...d7 when low. fetched the next fifo data byte (if available) from the receive fifo buffer when rd# goes from high to low. see section 3.6 for timing diagram. 9 wr input writes the data byte on the d0...d7 pins into the transmit fifo buffer when wr goes from high to low. see section 3.7 for timing diagram. 17 txe# output when high, do not write data into the fifo. when low, data can be written into the fifo by strobing wr high, then low. during reset this signal pin is tri - state. see section 3.7 for timing diagram. 18 rxf # output when high, do not read data from the fifo. when low, there is data available in the fifo which can be read by strobing rd# low, then high again. during reset this signal pin is tri - state. see section 3.6 for timing diagram. if the remote wakeup option is enabled in the internal mtp memory , during usb suspend mode (pwren# = 1) rxf# becomes an input. this can be used to wake up the usb host from su spend mode by strobing this pin low for a minimum of 20ms which will cause the device to request a resume on the usb bus. table 3 . 8 fifo interface group (see note 2 ) notes: when used in input mode, the input pins are pulled to vccio via internal 200k resistors. these pins can be programmed to gently pull low during usb suspend (pwren# = 1) by setting an option in the internal mtp memory .
copyright ? 201 3 future technology devices international limited 11 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 3.5 cbus signal options the following options can be configured on the cbus i/o pins. cbus signal options are common to both package versions of the ft240x . these options can be configured in the internal mtp memory using the software utility ft_pprog, which can be downloaded fro m the ftdi utilities ( www.ftdichip.com ) . the default configuration is described in section 8 . cbus signal option available on cbus pin description tri - state cbus5 , cbus 6 io pad is tri - stated drive 1 cbus5 , cbus 6 output a constant 1 drive 0 cbus5 , cbus 6 output a constant 0 pwren# cbus5 , cbus 6 output is low after the device has been configured by usb, then high during usb suspend mode. this output can be used to control power to external logic p - channel logic level mosfet switch. enable the interface pull - down option when using the pwren# in thi s way. sleep# cbus5 , cbus 6 goes low during usb suspend mode. typically used to power down an external ttl to rs232 level converter ic in usb to rs232 converter designs. clk24 mhz cbus5 , cbus 6 24 mhz clock output.* clk12 mhz cbus5 , cbus 6 12 mhz clock output.* clk6 mhz cbus5 , cbus 6 6 mhz clock output.* bcd charger cbus5 , cbus 6 battery charge detect, indicates when the device is connected to a dedicated battery charger host. active high output. bcd charger # cbus5 , cbus 6 inverse of bcd charger bitbang_wr# cbus5 , cbus 6 synchronous and asynchronous bit bang mode wr# strobe output. bitbang_rd# cbus5 , cbus 6 synchronous and asynchronous bit bang mode rd# strobe output. vbus sense cbus5 , cbus 6 input to detect when vbus is present. time stamp cbus5 , cbus 6 toggle signal which changes state each time a usb sof is received keep_awake# cbus5, cbus6 prevents the device from entering suspend state when unplugged. table 3 . 9 cbus configuration control *when in usb suspend mode the outputs clocks are also suspended.
copyright ? 201 3 future technology devices international limited 12 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 3.6 ft240x fifo read timing diagrams figure 3 . 3 fifo read cycle time description minimum maximum unit t1 rd# active pulse width 50 - ns t2 rd# to rd# pre - charge time 50 + t6 - ns t3 rd# active to valid data* 20 50 ns t4 valid data hold time from rd# inactive* 0 - ns t5 rd# inactive to rxf# 0 25 ns t6 rxf# inactive after rd cycle 80 - ns table 3 . 10 fifo read cycle timings *load = 30pf rxf# rd# d[7...0] t3 t1 t5 t6 t2 t4 valid data
copyright ? 201 3 future technology devices international limited 13 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 3.7 ft240x fifo write timing diagrams figure 3 . 4 fifo write cycle time description minimum maximum unit t7 wr active pulse width 50 - ns t8 wr to wr pre - charge time 50 - ns t9 valid data setup to wr falling edge* 20 - ns t10 valid data hold time from wr inactive* 0 - ns t11 wr inactive to txe# 5 25 ns t12 txe# inactive after wr cycle 80 - ns table 3 . 11 fifo write cycle *load = 30pf valid data d[7...0] wr txe# t7 t12 t11 t8 t9 t10
copyright ? 201 3 future technology devices international limited 14 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 4 function description the ft240x is a usb to parallel fifo interface device which simplifies usb implementations and reduces external component count by fully integrating into the device an mtp memory and an integrated clock circuit which requires no external crystal. it has been designed to operate efficiently with usb host controller s by using as little bandwidth as possible when compared to the total usb bandwidth available. 4.1 key features functional integration. fully integrated mtp memory , clock generation, avcc filtering, power - on - reset (por) and ldo regulator. configurable cbus i/o pin options. the fully integr ated mtp memory allows configuration of the control bus (cbus) functionality and drive strength selection. there are 2 configurable cbus i/o options. the configurable options are defined in section 3.5. the cbus lines can be configured with any one of the se output options by setting bits in the internal mtp memory . the device is shipped with the most commonly used pin definitions pre - programmed - see section 8 for d etails. asynchronous bit bang mode. in asynchronous bit - bang mode, the eight fifo lines can be switched from the regular interface mode to an 8 - bit general purpose i/o port. data packets can be sent to the device and they will be sequentially sent to the i nterface at a rate controlled by an internal timer (equivalent to the baud rate pre - scaler . this option will be described more fully in a separate application note available from ftdi website ( www.ftdichip.com ) . synchronous bit bang mode. the ft240x supports synchronous bit bang mode. this mode differs from asynchronous bit bang mode in that the interface pins are only read when the device is written to. thi s makes it easier for the controlling program to measure the response to an output stimulus as the data returned is synchronous to the output data. an application note, an232r - 01 , available from ftdi website ( www.ftdichip.com ) describes this feature. high output drive option. the parallel fifo interface and the four fifo handshake pins can b e made to drive out at three times the standard signal drive level thus allowing multiple devices to be driven, or devices that require a greater signal drive strength to be interfaced to the ft240x . this option is configured in the internal mtp memory . pr ogrammable fifo rx buffer timeout. the fifo rx buffer timeout is used to flush remaining data from the receive buffer. this timeout defaults to 16ms, but is programmable over usb in 1ms increments from 2ms to 255ms, thus allowing the device to be optimised for protocols that require fast response times from short data packets. wake up function. if usb is in suspend mode, and remote wake up has been enabled in the internal mtp memory (it is enabled by default) . strobing the siwu# pin low for a minimum of 20m s will cause the ft240x to request a resume from suspend on the usb bus. normally this can be used to wake up the host pc from suspend. source power and power consumption . the ft2 40 x is capable of operating at a voltage supply between + 3.3 v and +5 .25 v with a nominal operational mode current of 8 ma and a nominal usb suspend mode current of 125 a. this allows greater margin for peripheral designs to meet the usb suspend mode current limit of 2.5ma . an integrated level converter within allows the ft2 40 x to interface to logic running at +1.8v to +3.3v (5v tol erant ).
copyright ? 201 3 future technology devices international limited 15 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 4.2 functional block descriptions the following paragraphs detail each function within the ft240x . please refer to the block diagram shown in figure 2 . 1 . internal mtp memory . the internal mtp memory in the ft240x is used to store usb vendor id (vid), product id (pid), device serial number, product description string and various other usb configuration descriptors. the ft240x is supplied with the internal mtp memory pre - programmed as described in section 8 . a user area of the internal mtp memory is available to system designers to allow storing additional data from the user application over usb . the internal mtp memory descriptors can be programmed in circuit, over usb without any addi tional voltage requirement. the descriptors can be programmed using the ftdi utility software called ft_prog, which can be downloaded from ftdi utilities on the ftdi website ( www.ftdichip.com ) . +1.8 v ldo regulator. the + 1.8 ldo regulator generates the + 1.8v reference voltage for driving the internal core of the ic. +3.3v ldo regulator. the +3.3v ldo regulator generates the +3.3v reference voltage for driving the usb transceiver cell output buffers. it requires an external decoupling capacitor to be attached to the 3v3out regulator output pin. it also provides +3.3v power to the 1.5k internal pull up resistor on usbdp. the main function of the ldo is t o power the usb transceiver and the reset generator cells rather than to power external logic. however, it can be used to supply external circuitry requiring a +3.3v nominal supply with a maximum current of 50ma. usb transceiver. the usb transceiver cell p rovides the usb 1.1 / usb 2.0 full - speed physical interface to the usb cable. the output drivers provide +3.3v level slew rate control signalling, whilst a differential input receiver and two single ended input receivers provide usb data in, single - ended - 0 (se0) and usb reset detection conditions respectfully. this function also incorporates a 1.5k pull up resistor on usbdp. the block also detects when connected to a usb power supply which will not enumerate the device but still supply power and may be use d for battery charging. usb dpll. the usb dpll cell locks on to the incoming nrzi usb data and generates recovered clock and data signals for the serial interface engine (sie) block. internal 12mhz oscillator. the internal 12mhz oscillator cell generates a 12mhz reference clock. this provides an input to the x4 clock multiplier function. the 12mhz oscillator is also used as the reference clock for the sie, usb protocol engine and fifo controller blocks. clock multiplier / divider. the clock multiplier / div ider takes the 12mhz input from the internal oscillator function and generates the 48mhz. the 48mz clock reference is used by the usb dpll and the baud rate generator blocks. serial interface engine (sie). the serial interface engine (sie) block performs t he parallel to serial and serial to parallel conversion of the usb data. in accordance with the usb 2.0 specification, it performs bit stuffing/un - stuffing and crc5/crc16 generation. it also verifies the crc on the usb data stream. usb protocol engine. the usb protocol engine manages the data stream from the device usb control endpoint. it handles the low level usb protocol requests generated by the usb host controller and the commands for controlling the functional parameters of the fifo in accordance w ith the usb 2.0 specification section 9 . fifo rx buffer ( 512 bytes). data sent from the usb host controller to the fifo via the usb data out endpoi nt is stored in the fifo rx (receive) buffer and is removed from the buffer by reading the contents of the fifo using the rd# pin. (rx relative to the usb interface). fifo tx buffer ( 512 bytes). data written into the fifo using the wr pin is stored in the fifo tx (transmit) buffer. the usb host controller removes data from the fifo tx buffer by sending a usb request for data from the device data in endpoint. (tx relative to the usb interface). fifo controller with programmable high drive. the fifo controlle r handles the transfer of data between the fifo rx, the fifo tx buffers and the external fifo interface pins (d0 - d7). additionally, the fifo signals have a configurable high drive strength capability which is configurable in the mtp memory . reset gener ator. the integrated reset generator cell provides a reliable power - on reset to the device internal circuitry at power up. the reset# input pin allows an external device to reset the ft240x . reset# can be tied to vcc or left unconnected if not being used.
copyright ? 201 3 future technology devices international limited 16 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 5 devices characteristics and ratings 5.1 absolute maximum ratings the absolute maximum ratings for the ft240x devices are as follows. these are in accordance with the absolute maximum rating system (iec 60134). exceeding these may cause permanent damage to th e device. parameter value unit conditions storage temperature - 65c to 150c degrees c floor life (out of bag) at factory ambient (30c / 60% relative humidity) 168 hours (ipc/jedec j - std - 033a msl level 3 compliant)* hours ambient operating temperature (power applied) - 40c to 85c degrees c mttf ft2 4 0x s tbd hours mttf ft2 4 0x q tbd hours vcc supply voltage - 0.3 to +5 . 5 v vccio io voltage - 0.3 to +4.0 v dc input voltage C usbdp and usbdm - 0.5 to +3.63 v dc input voltage C high impedance bi - directionals (powered from vccio) - 0.3 to +5.8 v dc output current C outputs 22 ma table 5 . 1 absolute maximum ratings * if devices are stored out of the packaging beyond this time limit the devices should be baked before use. the devices should be ramped up to a temperature of +125 c and baked for up to 17 hours . 5.2 esd and latch - up specifications description specification human body mode (hbm) > 2kv machine mode (mm) > 200v charged device mode (cdm) > 500v latch - up > 200ma table 5 . 2 esd and latch - up specifications
copyright ? 201 3 future technology devices international limited 17 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 5.3 dc characteristics dc characteristics (ambient temperature = - 40c to +85c) parameter description minimum typical maximum units conditions vcc vcc operating supply voltage 2.97 5 5.5 v normal operation vcc 2 vccio operating supply voltage 1.62 --- 3.63 v icc1 operating supply current 8 8 8.4 ma normal operation icc2 operating supply current 125 a table 5 . 3 operating voltage and current
copyright ? 201 3 future technology devices international limited 18 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 parameter description minimum typical maximum units conditions voh output voltage high 2.97 vccio vccio v ioh = +/ - 2ma i/o drive strength* = 4ma 2.97 vccio vccio v i/o drive strength* = 8ma 2.97 vccio vccio v i/o drive strength* = 12ma 2.97 vccio vccio v i/o drive strength* = 16ma vol output voltage low 0 0.4 v iol = +/ - 2ma i/o drive strength* = 4ma 0 0.4 v i/o drive strength* = 8ma 0 0.4 v i/o drive strength* = 12ma 0 0.4 v i/o drive strength* = 16ma vil input low switching threshold 0.8 v lvttl vih input high switching threshold 2.0 v lvttl vt switching threshold 1. 49 v lvttl vt - schmitt trigger negative going threshold voltage 1.1 5 v vt+ schmitt trigger positive going threshold voltage 1.6 4 v rpu input pull - up resistance 40 75 190 k? vin = 0 rpd input pull - down resistance 40 75 190 k? vin =vccio iin input leakage current - 10 +/ - 1 10 a vin = 0 ioz tri - state output leakage current - 10 +/ - 1 10 a vin = 5.5v or 0 table 5 . 4 fifo i/o p in characteristics vccio = + 3.3 v, (except usb phy pins) * the i/o drive strength and slow slew - rate are configurable in the mtp memory .
copyright ? 201 3 future technology devices international limited 19 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 parameter description minimum typical maximum units conditions voh output voltage high 2.25 vccio vccio v ioh = +/ - 2ma i/o drive strength* = 4ma 2.25 vccio vccio v i/o drive strength* = 8ma 2.25 vccio vccio v i/o drive strength* = 12ma 2.25 vccio vccio v i/o drive strength* = 16ma vol output voltage low 0 0.4 v iol = +/ - 2ma i/o drive strength* = 4ma 0 0.4 v i/o drive strength* = 8ma 0 0.4 v i/o drive strength* = 12ma 0 0.4 v i/o drive strength* = 16ma vil input low switching threshold 0.8 v lvttl vih input high switching threshold 0.8 v lvttl vt switching threshold 1.1 v lvttl vt - schmitt trigger negative going threshold voltage 0.8 v vt+ schmitt trigger positive going threshold voltage 1. 2 v rpu input pull - up resistance 40 75 190 k? vin = 0 rpd input pull - down resistance 40 75 190 k? vin =vccio iin input leakage current - 10 +/ - 1 10 a vin = 0 ioz tri - state output leakage current - 10 +/ - 1 10 a vin = 5.5v or 0 table 5 . 5 fifo i/o p in characteristics vccio = +2.5 v, (except usb phy pins) * the i/o drive strength and slow slew - rate are configurable in the mtp memory .
copyright ? 201 3 future technology devices international limited 20 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 parameter description minimum typical maximum units conditions voh output voltage high 1.62 vccio vccio v ioh = +/ - 2ma i/o drive strength* = 4ma 1.62 vccio vccio v i/o drive strength* = 8ma 1.62 vccio vccio v i/o drive strength* = 12ma 1.62 vccio vccio v i/o drive strength* = 16ma vol output voltage low 0 0.4 v iol = +/ - 2ma i/o drive strength* = 4ma 0 0.4 v i/o drive strength* = 8ma 0 0.4 v i/o drive strength* = 12ma 0 0.4 v i/o drive strength* = 16ma vil input low switching threshold 0.77 v lvttl vih input high switching threshold 1.6 v lvttl vt switching threshold 0.77 v lvttl vt - schmitt trigger negative going threshold voltage 0.557 v vt+ schmitt trigger positive going threshold voltage 0.893 v rpu input pull - up resistance 40 75 190 k? vin = 0 rpd input pull - down resistance 40 75 190 k? vin =vccio iin input leakage current - 10 +/ - 1 10 a vin = 0 ioz tri - state output leakage current - 10 +/ - 1 10 a vin = 5.5v or 0 table 5 . 6 fifo i/o pin characteristics vccio = +1.8 v (except usb phy pins) * the i/o drive strength and slow slew - rate are configurable in the mtp memory
copyright ? 201 3 future technology devices international limited 21 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 parameter description minimum typical maximum units conditions voh output voltage high vcc - 0.2 v vol output voltage low 0.2 v vil input low switching threshold - 0.8 v vih input high switching threshold 2.0 - v table 5 . 7 usb i/o pin (usbdp, usbdm) characteristics 5.4 mtp m emory reliability characteristics the internal 2048 b yte mtp memory has the following reliability characteristics: parameter value unit data retention 1 0 years write cycle 2 ,000 cycles read cycle unlimited cycles table 5 . 8 mtp m emory characteristics 5.5 internal clock characteristics the internal clock oscillator has the following characteristics: parameter value unit minimum typical maximum frequency of operation (see note 1) 11.98 12.00 12.02 mhz clock period 83.19 83.33 83.47 ns duty cycle 45 50 55 % table 5 . 9 internal clock characteristics note 1: equivalent to +/ - 1667ppm
copyright ? 201 3 future technology devices international limited 22 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 6 usb power configurations the following sections illustrate possible usb power configurations for the ft240x . the illustrations have omitted pin numbers for ease of understanding since the pins differ between the ft240xs and ft240x q package options. all u sb power configurations illustrated apply to both package options for the ft240x device. please refer to section 0 for the package option pin - out an d signal descriptions. 6.1 usb bus powered configuration figure 6 . 1 bus powered configuration figure 6 . 1 i llustrates the ft240x in a typical usb bus powered design configuration. a usb bus powered device gets its power from the usb bus. basic rules for usb bus power devices are as follows C i) on plug - in to usb, the device should draw no more current than 100ma. ii) in usb suspend mode the device should draw no more than 2.5ma. iii) a bus powered high power usb device (one that draws more than 100ma) should use the pwren# to keep the current below 100ma on plug - in and 2.5ma on usb suspend. iv) a device that consumes more than 100ma cannot be plugged into a usb bus powered hub. v) no device can draw more than 500ma from the usb bus. the power descriptors in the internal mtp memory of the ft240x should be programmed to match the current drawn by the device. a ferrite bead is connected in series with the usb power supply to reduce emi noise from the ft240x and associated circuitry being radiated down the usb cable to the usb host. the value of the ferrite bead depends on the total current drawn by the application. a suitable range of ferrite beads is available from steward ( www.steward.com ) , for example steward part # mi0805k 601 r - 10. f t 2 4 0 x 1 2 3 4 5 s h i e l d f e r r i t e b e a d g n d g n d v c c g n d v c c 3 v 3 o u t u s b d m u s b d p v c c i o v c c a g n d g n d r e s e t # 1 0 0 n f 1 0 0 n f 1 0 n f 4 . 7 u f + 2 7 r 2 7 r g n d 4 7 p f 4 7 p f
copyright ? 201 3 future technology devices international limited 23 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 6.2 self powered configuration figure 6 . 2 self powered configuration figure 6 . 2 illustrates the ft240x in a typical usb self powered configuration. a usb self powered device gets its power from its own power supply, vcc, and does not draw current from the usb bus. the ba sic rules for usb self powered devices are as follows C i) a self powered device should not force current down the usb bus when the usb host or hub controller is powered down. ii) a self powered device can use as much current as it needs during normal operation and usb suspend as it has its own power supply. iii) a self powered device can be used with any usb host, a bus powered usb hub or a self powered usb hub. the power descriptor in the internal mtp memory of the ft240x should be programmed to a value of zero (self powered). in order to comply with the first requirement above, the usb bus power (pin 1) is used to control the vbus_sense pin of the f t24 0x device. when the usb host or hub is powered up an internal 1.5k resistor on usbdp is pulled up to +3.3v, thus identifying the device as a full speed device to the usb host or hub. when the usb host or hub is powered off, vbus_sense pin will be low and the f t24 0x is held in a suspend state. in this state the internal 1.5k resistor is not pulled up to any power supply (hub or host is powered down), so no current flows down usbdp via the 1.5k pull - up resistor. failure to do this may cause some usb host or hub controllers to power up erratically. figu re 6 . 3 illustrates a self powered design which has a + 3.3 v to +5.25v supply. note: 1. when the ft2 40x is in reset, the interface i/o pins are tri - stated. input pins have internal 200k pull - up resistors to vcc io, so they will gently pull high unless driven by some external logic. f t 2 4 0 x 1 2 3 4 5 s h i e l d g n d g n d v c c g n d v c c 3 v 3 o u t u s b d m u s b d p v c c i o v c c ( 3 . 3 - 5 . 2 5 v ) a g n d g n d r e s e t # 1 0 0 n f 1 0 0 n f 1 0 0 n f 4 . 7 u f + g n d 4 k 7 1 0 k 2 7 r 2 7 r g n d 4 7 p f 4 7 p f v b u s _ s e n s e
copyright ? 201 3 future technology devices international limited 24 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 6.3 usb bus powered with power switching configuration figure 6 . 4 bus powered with power switching configuration a requirement of usb bus powered applications, is when in usb suspend mode the application draws a total current of less than 2.5ma. this requirement includes external logic. some external logic has the ability t o power itself down into a low current state by monitoring the pwren# signal. for external logic that cannot power itself down in this way, the ft240x provides a simple but effective method of turning off power during the usb suspend mode. figure 6 . 4 shows an example of using a discrete p - channel mosfet to control the power to external logic. a sui table device to do this is an international rectifier (www.irf.com) irlml6402, or equivalent . it is recommended that a soft start circuit consisting of a 1k series resistor and a 0.1f capacitor is used to limit the current surge when the mosfet turns on. without the soft start circuit it is possible that the transient power surge, caused when the mosfet switches on, will reset the ft240x or the usb host/hub controller. the soft start circuit example shown in figure 6 . 4 powers up w ith a slew rate of approximaely12.5v/ms. thus supply voltage to external logic transitions from gnd to +5v in approximately 400 microseconds. as an alternative to the mosfet, a dedicated power switch ic with inbuilt soft - start can be used. a suitable pow er switch ic for such an application is the micrel ( www.micrel.com ) mic2025 - 2bm or equivalent. with power switching controlled designs the following should be noted: i) the external logic to which the power is being switched should have its own reset circuitry to automatically reset the logic when power is re - applied when moving out of suspend mode. ii) set the pull - down on suspend option in the in ternal ft240x mtp memory . iii) the pwren# pin should be used to switch the power to the external circuitry. iv) for usb high - power bus powered applications (one that consumes greater than 100ma, and up to 500ma of current from the usb bus), the power consumption of the application must be set in the max power field in the internal ft240x mtp memory . a high - power bus powered application uses the descriptor in the internal ft240x mtp memory to inform the system of its power requirements. v) pwren# gets its vcc from vccio. for designs using 3v3 logic, ensure vccio is not powered down using the external logic. in this case use the +3v3out. f t 2 4 0 x 1 2 3 4 5 s h i e l d f e r r i t e b e a d g n d g n d v c c g n d v c c 3 v 3 o u t u s b d m u s b d p v c c i o a g n d g n d r e s e t # 1 0 0 n f 1 0 0 n f 1 0 n f 4 . 7 u f + c b u s 5 p w r e n # 1 0 k 1 k s w i t c h e d 5 v p o w e r t o e x t e r n a l l o g i c 0 . 1 u f 0 . 1 u f p c h a n n e l p o w e r m o s f e t 2 7 r 2 7 r 4 7 p f 4 7 p f
copyright ? 201 3 future technology devices international limited 25 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 7 application examples the following sections illustrate possible applications of the ft240x . the illustrations have omitted pin numbers for ease of understanding since the pins differ between the ft240xs and ft240x q package options. 7.1 usb to mcu fifo interface figure 7 . 1 usb to mcu fifo interface a typical example of using the ft240x as a usb to microcontroller (mcu) fifo interface is illustrated in figure 7 . 1 . this example uses two mcu i/o ports: one port (8 bits) to transfer data and the other port (4 or 5 bits) to monitor the txe# and rxf# status bits and generate the rd# and wr strobes to the f t240x , when required. using pwren# for this function is optional. a g n d g n d 1 0 0 n f 3 v 3 o u t v c c i o r e s e t # + 1 0 0 n f 4 . 7 u f v c c d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 r x f # w r # r d # t x e # u s b d p u s b d m v c c 1 2 3 4 5 p w r e n # m i c r o c o n t r o l l e r i / o 1 0 i / o 1 1 i / o 1 2 i / o 1 3 f e r r i t e b e a d g n d g n d g n d + g n d 1 0 n f v c c i / o 1 4 i / o 1 5 i / o 1 6 i / o 1 7 i / o 2 0 i / o 2 1 i / o 2 2 i / o 2 3 i / o 2 4 v c c 1 0 k s h i e l d v c c f t 2 4 0 x 2 7 r 2 7 r 4 7 p f 4 7 p f u s b d m g n d u s b d p
copyright ? 201 3 future technology devices international limited 26 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 7.2 battery charge detection a recent addition to the usb specification ( http://www.usb.org/developers/devclass_d ocs/bcv1.2_011912.zip ) is to allow for additional charging profiles to be used for charging batteries in portable devices. these charging profiles do not enumerate the usb port of the peripheral . t he ft2 40 x device will detect that a usb compliant dedicated charging port (dcp) is connected. once detected while in suspend mode a battery charge detection signal is provided to allow external logic to switch to charging mode as opposed to operation mode. figure 7 . 2 usb battery charging detection (1 pin) to use the ft240x with battery charging detection the cbus pins must be reprogrammed to allow for the bcd charger output to switch the external charger circuitry on. the cbus pin s are configured in the internal mtp memory with the free utility ftprog. if the charging circuitry requires an active low signal to enable it, the cbus pin can be programmed to bcd charger# as an alternative. when connected to a usb compliant dedicated ch arging port (dcp, as opposed to a standard usb host) the device usb signals will be shorted together and the device suspended. the bcd charger signal will bring the ltc4053 out of suspend and allow battery charging to start. the charge current in the examp le above is 1a as defined by the resistance on the prog pin. alternatively the pwren# and sleep pins may be used to control the ltc4053 such that a battery may be charged from a standard host (low current) or from a dedicated charging port (high current). in such a design as shown above the charge current would need to be limited to 0.4a to ensure that the usb host power limit is not exceeded. x - c h i p p i n f u n c t i o n e e p r o m s e t t i n g c b u s 0 b c d b a t t e r y o p t i o n s b a t t e r y c h a r g e r e n a b l e f o r c e p o w e r e n a b l e d e - a c t i c a t e s l e e p x g n d g n d 0 . 1 u f 0 . 1 u f g n d g n d 6 0 0 r / 2 a 1 0 n f v b u s 3 v 3 o u t 0 . 1 u f 0 r g n d s l d g n d 2 7 r 2 7 r v b u s 1 d - 2 d + 3 g n d 5 i d 4 c n u s b v c c 2 f a u l t 3 t i m e r 4 g n d 5 n t c 6 p r o g 7 s h d n 8 b a t 9 a c p r 1 0 c h r g 1 g n d 1 1 l t c 4 0 5 3 e d d g n d 3 v 3 o u t 3 v 3 o u t 4 . 7 u f 0 . 1 u f g n d v b u s v b u s g n d v b a t t g n d g n d 1 k 5 g n d 1 t b 3 . 5 m m v b u s v b u s n t c 0 . 1 u f g n d v b u s 1 u f 1 r g n d v b u s b c d 2 k 2 g n d j p 1 1 - 2 2 - 3 n c t e n a b l e d n c t a v a i l a b l e j p 1 s i p - 3 n t c g n d n c t d i s a b l e d ( d e f a u l t ) j u m p e r - 2 m m 4 k 3 2 1 % g n d d p d m 3 v 3 o u t r e s e t # v c c g n d c b u s 0 v c c i o f t 2 4 0 x b c d 1 a w h e n c o n n e c t e d t o a d e d i c a t e d c h a r g e r p o r t 0 a w h e n e n u m e r a t e d 0 a w h e n i n s l e e p 0 a w h e n n o t e n u m e r a t e d a n d n o t i n s l e e p + - n c t n . f .
copyright ? 201 3 future technology devices international limited 27 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 figure 7 . 3 usb battery charging detection (2 pin) in the example above the ft240x sleep pin is used to enable/disable the ltc4053, while the pwren# signal alters the charging current by altering the resistance on the ltc4053 prog pin. to calculate the equivalent resistance on the ltc4053 prog pin select a charge current, then res = 1500v/i chg for more configuration options of the ltc4053 refer to: an_175_battery charging over usb note: if the ft 240 x is connected to a standard host port such that the device is enumerated the batter y charge detection signal is inactive as the device will not be in suspend. x - c h i p p i n f u n c t i o n e e p r o m s e t t i n g c b u s 5 c b u s 6 s l e e p # p w r e n # b a t t e r y o p t i o n s b a t t e r y c h a r g e r e n a b l e f o r c e p o w e r e n a b l e d e - a c t i c a t e s l e e p x x x s l e e p # p w r e n # d p d m 3 v 3 o u t v c o r e r e s e t # v c c c b u s 6 c b u s 5 v c c i o u 1 f t 2 4 0 x 0 . 4 a w h e n c o n n e c t e d t o a d e d i c a t e d c h a r g e r p o r t g n d g n d 0 . 1 u f 0 . 1 u f g n d g n d 6 0 0 r / 2 a 1 0 n f v b u s 3 v 3 o u t 0 . 1 u f 0 r g n d s l d g n d 2 7 r 2 7 r v b u s 1 d - 2 d + 3 g n d 5 i d 4 c n u s b 3 v 3 o u t 3 v 3 o u t v b u s v b u s n . f . 1 6 k 5 1 % g n d 4 k 3 2 1 % p w r e n # 0 . 4 a w h e n e n u m e r a t e d 0 a w h e n i n s l e e p m o d e 0 . 1 a w h e n n o t e n u m e r a t e d a n d n o t i n s l e e p m o d e v c c 2 f a u l t 3 t i m e r 4 g n d 5 n t c 6 p r o g 7 s h d n 8 b a t 9 a c p r 1 0 c h r g 1 g n d 1 1 l t c 4 0 5 3 e d d g n d 4 . 7 u f 0 . 1 u f g n d v b u s v b u s g n d v b a t t g n d g n d 1 t b 3 . 5 m m n t c 0 . 1 u f g n d v b u s 1 u f 1 r g n d v b u s 2 k 2 g n d j p 1 1 - 2 2 - 3 n c t e n a b l e d n c t a v a i l a b l e j p 1 s i p - 3 n t c g n d n c t d i s a b l e d ( d e f a u l t ) j u m p e r - 2 m m 4 k 3 2 1 % + - n c t s l e e p #
copyright ? 201 3 future technology devices international limited 28 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 8 i nternal mtp m emory configuration the ft240x includes an internal mtp memory which holds the usb configuration descriptors, other configuration data for the chip and also user dat a areas. following a power - on reset or a usb reset the ft240x will scan its internal mtp memory and read the usb configuration descriptors stored there. in many cases, the default values programmed into the mtp memory will be suitable and no re - programming will be necessary. the defaults can be found in section 8.1 . the mtp memory in the ft240x can be programmed over usb if the values need to be changed for a particular application. further details of this are provided from section 8.2 onwards. users who do not have their own usb vendor id but who would like to use a unique product id in their design can apply to ftdi for a free block of unique pids. see tn_100 C usb vendor id/product id guidelines for more details . 8.1 default values the default factory programmed values of the internal mtp memory are shown in table 8 . 1 . parameter value notes usb vendor id (vid) 0403h ftdi default vid (hex) usb product ud (pid) 6015 h ftdi default pid (hex) serial number enabled yes serial number see note a unique serial number is generated and programmed into the mtp memory during device final test. pull down i/o pins in usb suspend disabled enabling this option will make the device pull down on the fifo interface lines when in usb suspend mode (pwren# is high). manufacturer name ftdi product description ft240x usb fifo max bus power current 90ma power source bus powered device type ft240x usb version 0200 returns usb 2.0 device description to the host. note: the device is a usb 2.0 full speed device (12mb/s) as opposed to a usb 2.0 high speed device (480mb/s). remote wake up d is abled taking siwu # low will wake up the usb host controller from suspend in approximately 20 ms. when enabled. dbus drive current strength 4ma options are 4ma, 8ma, 12ma, 16ma dbus slew rate slow options are slow or fast
copyright ? 201 3 future technology devices international limited 29 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 parameter value notes dbus schmitt trigger enable normal options are normal or schmitt cbus drive current strength 4ma options are 4ma, 8ma, 12ma, 16ma cbus slew rate slow options are slow or fast cbus schmitt trigger enable normal options are normal or schmitt high current i/os disab led enables the high drive level on the fifo data bus and control i/o pins. load vcp driver disabled enabling this will load the vcp driver interface for the device. cbus5 vbus_sense used to detect when the device is connected to a usb host and power is available. cbus6 keep _ awake# prevents the device from entering suspend state when unplugged. table 8 . 1 default internal mtp memory configuration 8.2 methods of programming the mtp memory 8.2.1 programming the mtp memory over usb the mtp memory on all ft - x devices can be programmed over usb. this method is the same as for the eeprom on other ftdi devices such as the ft232r. no additional hardware, connections or programming voltages are required. the device is simpl y connected to the host computer in the same way that it would be for normal applications, and the ft_prog utility is used to set the required options and program the device. the ft _ prog utility is provided free - of - charge from the ftdi website, and can be found at the link below. the user guide is also available at this link. note that the ft - x devices require ft_prog version 2.5 or later. http://www.ftdichip.com/support/utilities.htm#ft_prog additionally, d2xx commands can be used to program the mtp memory from within user applications. for more information on the commands available, please see the d2xx programmers guide below. http://www.ftdichip.com/support/documents/programguides/d2xx_programmer's_guide(ft_000071).p df
copyright ? 201 3 future technology devices international limited 30 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 8.3 memory map the ft - x family mtp memory has various areas whi ch come under three main categories: ? user memory area ? configuration memory area (writable) ? configuration memory area (non - writable) memory area description word address user memory area 2 accessible via usb 0x3ff - 0x80 configuration memory area accessible via usb 0x7e - 0x50 configuration memory area can not be written 0x4e - 0x40 user memory area 1 accessible via usb 0x3e - 0x12 configuration memory area accessible via usb 0x10 - 0x00 figure 8 . 1 : simplified memory map for the ft - x user memory area the user memory areas are highlighted in green on the memory map. they can be read and written via usb on the ft240x. all locations within this range are freely programmable; no areas have special functions and there is no checksum for the user area. note that the application should take into account the specification for the number of write cycles in section 5.4 if it will be writing to the mtp memory multiple times. configuration memory area (writable) this area stores the configuration data for the device, including the data which is returned to the host in the configuration descriptors (e.g. the vid, pid and string descriptions) and also values which set the hardware configuration (the signal assigned to each cbus pin for example). these values can have a significant effect on the behaviour of the device. steps must be taken to ensure that these locations are not written to un - intentionally by an application which is intended to access only the user area. this area is included in a checksum which covers configuration areas of the memory, and so changing any value can also cause this checksum to fail. conf iguration memory area ( non - writable) this is a reserved area and the application should not write to this area of memory. any attempt to write these locations will fail.
copyright ? 201 3 future technology devices international limited 31 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 9 package parameters the ft240x is available in two different packages. the ft240xs is the ssop - 24 option and the ft240x q is the qfn - 24 package option. the solder reflow profile for both packages is described in section 9.5 . 9.1 ssop - 2 4 package mechanical dimensions figure 9 . 1 ssop - 2 4 package dimensions the ft240xs is supplied in a rohs compliant 2 4 pin ssop package. the package is lead (pb) free and uses a green compound. the package is fully compliant with european union directive 2002/95/ec. this pa ckage is nominally 8.66 mm x 3.91 mm body ( 8.66mm x 5.99 mm including pins). the pins are on a 0.6 3 5 mm pitch. the above mechanical drawing shows the ssop - 2 4 package. the date code format is yyxx where xx = 2 digit week number, yy = 2 digit year number. the code xxxxxxxxxxxx is the manufacturing lot code.
copyright ? 201 3 future technology devices international limited 32 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 9.2 ssop - 24 package markings figure 9 . 2 ssop - 2 4 package markings notes: 1. yyww = date code, where yy is year and ww is week number 2. marking alignment should be centre justified 3. laser marking should be used 4. all marking dimensions should be marked proportionally. marking font should be using greatek standard font (roman simplex) line 1 C ftdi logo l ine 2 C date code, revision l ine 3 C wafer lot number l ine 4 C ftdi part number f t 2 4 0 x s 1 1 2 1 3 2 4 - b
copyright ? 201 3 future technology devices international limited 33 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 9.3 qfn - 24 package mechanical dimensions figure 9 . 3 qfn - 24 package dimensions the ft240x q is supplied in a rohs compliant leadless qfn - 24 package - wqfn(x424), with pad size 114x114 . the package is lead ( pb ) free, and uses a green compound. the package is fully compliant with european union directive 2002/95/ec. this package is nominally 4. 0mm x 4. 0mm. the solder pads are on a 0.50mm pitch. the above me chanical drawing shows the qfn - 24 package. all dimensions are in millimetres. the centre pad on the base of the ft240x q is internally connected to gnd , and the pcb should not have tracking on the top layer in this area. the date code format is yyxx where xx = 2 digit week number, yy = 2 digit year number. the code xxxxxxx is the manufacturing lot code.
copyright ? 201 3 future technology devices international limited 34 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 9.4 qfn - 24 package markings figure 9 . 4 qfn - 24 package markings notes: 1. yyww = date code, where yy is year and ww is week number 2. marking alignment should be centre justified 3. laser marking should be used 4. all marking dimensions should be marked proportionally. marking font should be using greatek standard font (roman simplex) ft d i xxxxxxxxxx ft240xq line 1 C ftdi logo l ine 4 C date code, revision l ine 2 C wafer lot number 7 1 l ine 3 C ftdi part number yyww - b 12 18 19
copyright ? 201 3 future technology devices international limited 35 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 9.5 solder reflow profile the ft240x is supplied in pb free 24 ld ssop and qfn - 24 packages. the recommended solder reflo w profile for both package options is shown in 9.5 . figure 9 . 5 ft240x solder reflow profile the recommended values for the solder reflow profile are detailed in table 9 . 1 . values are shown for both a completely pb free solder process (i.e. the ft240x is used with pb free solder), and for a non - pb free solder process (i.e. the ft240x is used with non - pb free so lder). profile feature pb free solder process non - pb free solder process average ramp up rate (t s to t p ) 3c / second max. 3c / second max. preheat - temperature min (t s min.) - temperature max (t s max.) - time (t s min to t s max) 150c 200c 60 to 120 seconds 100c 150c 60 to 120 seconds time maintained above critical temperature t l : - temperature (t l ) - time (t l ) 217c 60 to 150 seconds 183c 60 to 150 seconds peak temperature (t p ) 260c 240c time within 5c of actual peak temperature (t p ) 20 to 40 seconds 20 to 40 seconds ramp down rate 6c / second max. 6c / second max. time for t= 25c to peak temperature, t p 8 minutes max. 6 minutes max. table 9 . 1 reflow profile parameter values critical zone: when t is in the range t to t t e m p e r a t u r e , t ( d e g r e e s c ) time, t (seconds) 25 p t = 25 o c to t t p t p t l t preheat s t l ramp up l p ramp down t max s t min s
copyright ? 201 3 future technology devices international limited 36 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 10 contact information head office C glasgow, uk future technology devices international limited unit 1, 2 seaward place, centurion business park glasgow g41 1hh united kingdom tel: +44 (0) 141 429 2777 fax: +44 (0) 141 429 2758 e - mail (sales) sales 1 @ftdichip.com e - mail (support) support 1 @ftdichip.com e - mail (general enquiries) admin1@ftdichip.com branch office C taipei, taiwan future technology devices international limited (taiwan) 2f, no. 516, sec. 1, neihu road taipei 114 taiwan , r.o.c. tel: +886 (0) 2 8791 3570 fax: +886 (0) 2 8791 3576 e - mail (sales) tw.sales1@ftdichip.com e - mail (support) tw.support1@ftdichip.com e - mail (general enquiries) tw.admin1@ftdichip.com branch office C hillsboro, oregon, usa future technology devices international limited (usa) 7130 sw fir loop tigard, or 97223 usa tel: +1 (503) 547 0988 fax: +1 (503) 547 0987 e - mail (sales) us.sales@ftdichip.com e - mail (support) us.support@ftdichip.com e - mail (general enquiries) us.admin@ftdichip.com branch office C shanghai, china future technology devices international limited (china) room 408, 317 xianxia road, shanghai, 200051 china tel: +86 21 62351596 fax: +86 21 62351595 e - mail (sales) cn.sales@ftdichip.com e - mail (support) cn.support@ftdichip.com e - mail (general enquiries) cn.admin@ftdichip.com web site http://ftdichip.com system and equipment manufacturers and designers are responsible to ensure that their systems, and any future technology devices international ltd (ftdi) devices incorporated in their systems, meet all applicable safety, regulatory and system - level per formance requirements. all application - related information in this document (including application descriptions, suggested ftdi devices and other materials) is provided for reference only. while ftdi has taken care to assure it is accurate, this informatio n is subject to customer confirmation, and ftdi disclaims all liability for system designs and for any applications assistance provided by ftdi. use of ftdi devices in life support and/or safety applications is entirely at the users risk, a nd the user agr ees to defend, indemnify and hold harmless ftdi from any and all damages, claims, suits or expense resulting from such use. this document is subject to change without notice. no freedom to use patents or other intellectual property rights is implied by the publication of this document. neither the whole nor any part of the information contained in, or the product described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright hol der. future technology devices international ltd, unit 1, 2 seaward place, centurion business park, glasgow g41 1hh, united kingdom. scotland registered company number: sc136640
copyright ? 201 3 future technology devices international limited 37 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 appendix a - references useful application notes http://www.ftdichip.com/documents/appnotes/an232r - 01_ft232rbitbangmodes.pdf http://www.ftdichip.com/documents/appnotes/an_107_advanceddriveroptions_an_00 0073.pdf http://www.ftdichip.com/documents/appnotes/an_121_ftdi_device_eeprom_user_area_usage.pdf http://www.ftdichip.com/documents/appnotes/an_120_aliasing_vcp_baud_rates.pdf http://www.ftdich ip.com/documents/appnotes/an_100_using_the_ft232_245r_with_external_osc(ft_ 000067).pdf http://www.ftdichip.com/resources/utilities/an_126_u ser_guide_for_ft232_factory%20test%20utility. pdf http://www.ftdichip.com/documents/appnotes/an232b - 05_baudrates.pdf http://www.ftdichip.com/documents/installguides.htm http://www.ftdichip.com/support/documents/technicalnotes/tn_100_usb_vid - pid_guidelines .pdf http://www.ftdichip.com/support/documents/appnotes/an_175_battery%20charging%20over%20usb %20with%20ftex%20devices.pdf http://www.usb.org/developers/devclass_docs/bcv1.2_011912.zip
copyright ? 201 3 future technology devices international limited 38 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 appendix b - list of figures and tables list of figures figure 2.1 ft240x block diagram ................................ ................................ ................................ ... 4 figure 3.1 ssop package pin out and schematic symbol ................................ ................................ ... 7 figure 3.2 qfn - 24 package pin out and schematic symbol ................................ ................................ 9 figure 3.3 fifo read cycle ................................ ................................ ................................ .......... 12 figure 3.4 fifo write cycle ................................ ................................ ................................ ......... 13 figure 6.1 bus powered configuration ................................ ................................ ........................... 22 figure 6.2 self powered configuration ................................ ................................ ........................... 23 figure 6.3 illustrates a self powered design which has a +3.3v to +5.25v supply. .............................. 23 figure 6.4 bus powered with power switching configuration ................................ ............................ 24 figure 7.1 usb to mcu fifo interface ................................ ................................ ........................... 25 figure 7.2 usb battery charging detection (1 pin) ................................ ................................ .......... 26 figure 7.3 usb battery charging detection (2 pin) ................................ ................................ .......... 27 figure 8.1: simplified memory map for the ft - x ................................ ................................ ............ 30 figure 9.1 ssop - 24 package dimensions ................................ ................................ ....................... 31 figure 9.2 ssop - 24 package markings ................................ ................................ .......................... 32 figure 9.3 qfn - 24 package dimensions ................................ ................................ ......................... 33 figure 9.4 qfn - 24 package markings ................................ ................................ ............................ 34 figure 9.5 ft240x solder reflow profile ................................ ................................ ......................... 35 list of tables table 3.1 usb interface group ................................ ................................ ................................ ....... 7 table 3.2 power and ground group ................................ ................................ ................................ . 7 table 3.3 miscellaneous signal group ................................ ................................ .............................. 8 table 3.4 fifo interface group (see note 2) ................................ ................................ .................... 8 table 3.5 usb interface group ................................ ................................ ................................ ....... 9 table 3.6 power and ground group ................................ ................................ ................................ . 9 table 3.7 miscellaneous signal group ................................ ................................ ............................ 10 table 3.8 fifo interface group (see note 2) ................................ ................................ .................. 10 table 3.9 cbus configuration control ................................ ................................ ........................... 11 table 3.10 fifo read cycle timings ................................ ................................ ............................. 12 table 3.11 fifo write cycle ................................ ................................ ................................ ......... 13 table 5. 1 absolute maximum ratings ................................ ................................ ............................ 16 table 5.2 esd and latch - up specifications ................................ ................................ .................... 16 table 5.3 operating voltage and current ................................ ................................ ....................... 17 table 5.4 fifo i/o pin characteristics vccio = +3.3v, (except usb phy pins) ................................ .. 18 table 5.5 fifo i/o pin characteristics vccio = +2.5v, (except usb phy pins) ................................ .. 19 table 5.6 fifo i/o pin characteristics vccio = +1.8v (except usb phy pins) ................................ ... 20 table 5.7 usb i/o pin (usbdp, usbdm) characteristics ................................ ................................ .. 21 table 5.8 mtp memory characteristics ................................ ................................ ........................... 21 table 5.9 internal clock characteristics ................................ ................................ ......................... 21
copyright ? 201 3 future technology devices international limited 39 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 table 8.1 default internal mtp memory configuration ................................ ................................ ..... 29 table 9.1 reflow profile parameter values ................................ ................................ ..................... 35
copyright ? 201 3 future technology devices international limited 40 ft240x usb 8 - bit fifo ic datasheet version 1.3 document no.: ft_000626 clearance no.: ftdi# 259 appendix c - revision history document title: usb 8 - bit fifo ic ft240x document reference no.: ft_000626 clearance no.: ftdi# 259 product page: http://www.ftdichip.com/ft - x.htm document feedback: send feedback version 1.0 initial da tasheet created 07/02/12 version 1.1 replaced vcc_core with vcore updated 24 pin ssop dimensions 22/02/12 version 1.2 clarified mtp reliability in table 5.8 17 /04/12 edited table 8 .1, changed load vcp driver to disabled version 1.2 removed references to led signals on the cbus pins 24 /09/ 2012 in table 3.9 as these are not available on the ft2 4 0 x. version 1.3 updated fron t page to clarify 5v tolerant 14/02/2013 updated tid updated us address

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